RE: RE: VIO pin connection

["Ingraham, Andrew" <Andrew.Ingraham@compaq.com>]

> Practically, sometimes motherboards are lying about there used signalling
> environment.
> On motherboards shipped today (don't name a vendor) you can see (measure)
> that the signalling level the chipset uses is 5 Volt (probably to be
> 'compatibel'
> with existing 5 Volt only PCI cards) but in contradiction the Vio Pin on
> the slot
> is saying that the signalling level should be 3.3 Volt.
 
I haven't heard of that combination.

But there were some publicized cases of "66 MHz PCI" motherboards (including
one by a very well known IC vendor) that used a 5V connector ... that is,
one with the physical key in the location for 5V signaling.  66 MHz PCI is
supposed to be 3.3V only.  Either someone "slipped up", or they cheated, so
that customers could plug their 5V cards into it.

Most "5V signaling" these days actually uses 3.3V levels, which is perfectly
acceptable because "5V signaling" is based on TTL levels where the minimum
Voh is only 2.4V.

> This also leads to additional clamping current you mentioned, because the
> asic
> assumes it should clamp to the 3.3 Volt Vio rail.
> 
> What do you think of this ?
 
It is, indeed, not a pretty situation.

But it doesn't justify violating one spec to fix someone else's screw-up.
Most people do play by the rules, and you shouldn't tailor yours for those
few motherboards (or plug-in cards) that pretend to be PCI but really
aren't.

The overshoot clamping is important not only for IC protection at 3.3V-only
ASICs, but also -- perhaps more importantly -- to control signal integrity.
Without it, rising edges ring more, and swing back down below a valid
Vih(min) and take a very long time to settle to a valid level.  The
motherboard designer counted on those clamps being there and working
correctly.  Not having them opens up the possibility of data corruption or
of a system that won't boot.

Regards,
Andy