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memory commands

** Proprietary **

hi,
I have some doubts over memory commands designing to tareget only core.
is it required  to design cache line for target.what is the difference between MRL,MRM and MR.how to implement these commands with targt.
I will be very thankful if somebody could answer my doubts.

bye
venkat.v

VENKAT.V
DESIGN ENGINEER(ASIC/FPGA)
EMSYS,L&T
e-mail:-vv@myw.ltindia.com
           venky_bel@yahoo.com
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