RE: Purposeful Parity control

[Kevin Normoyle <kbn@gluon.Eng.Sun.COM>]

In terms of what makes PCI difficult, we should leave
the parity discussion way behind, and talk about
the irdy/trdy negotiation for every data transfer.

that's what made pci timing hard. and with the transistor
densities available at the time frame, it was silly trying
to micro-optimize at that level, as opposed to having 
fixed size bursts.

The amount of mental energy, translated to dollars, that
has been wasted, because of that spec decision is staggering.

A proper spec would have eliminated  the need for AGP/PCI-X..in
fact the AGP/PCI combination is an embarassing bandaid....How
do you explain that? ...just by: That's how it goes. There are
other considerations beyond making a bus available to every 
mom and pop shop.

Of course, the garage shop guy wouldn't want fifos, so maybe
the single data beat negotiation is a good thing, even if you
can' meet 33mhz timing...(just run at 20mhz I guess...nice if
you have no performance requirements)

-kevin

> From pci-sig-request@znyx.com Wed Apr 18 05:18:00 2001
> Resent-Date: Wed, 18 Apr 2001 05:02:49 -0700
> To: pci-sig@znyx.com
> Subject: RE: Purposeful Parity control
> X-MIMETrack: Itemize by SMTP Server on rollsroyce/Znyx(Release 5.0.7 |March 21, 2001) at
>  04/18/2001 04:45:06 AM,
> 	Serialize by Router on rollsroyce/Znyx(Release 5.0.7 |March 21, 2001) at 04/18/2001
>  04:45:07 AM,
> 	Serialize complete at 04/18/2001 04:45:07 AM
> Resent-Message-ID: <yp9IbB.A.dlD.qqX36@electra>
> Resent-From: pci-sig@znyx.com
> X-Mailing-List: <pci-sig@znyx.com> archive/latest/7971
> X-Loop: pci-sig@znyx.com
> Resent-Sender: pci-sig-request@znyx.com
> 
> >This has denegrated right down to me level...
> >
> >Parity was and remains useful to detect fatal, data corruption, so
> >that corruption isn't silent, which is an even worse sin
> >than non-detected corruption.
> 
> I want to point out that PCI spec does not require the ASICs to parity
> check their internal datapaths, and I bet none do.  They contain bits
> that can be flipped by cosmic ray, and they contain transistors with
> gate oxide that can trap and retain cosmic ray induced electrons which
> shift their threshold voltage over time.  But there is no thought of
> doing parity check in them.
> 
> The real reason parity was added to the PCI bus is that customers
> demand it.  We engineers understand its true value or lack of, but the
> customers demand it even though they don't understand it.  But, as we
> all know, customers are always right.  That is wrong, but as I have
> said before, that is the way it is.  It is all politics.  On the other
> hand, the spec could have satisfied that demand without making it
> difficult for an FPGA implementation by pipelining parity by one clock
> cycle.
> 
>