RE: Purposeful Parity control

[Ross Harvey <ross@ghs.com>]

> From: Kevin Normoyle <kbn@gluon.Eng.Sun.COM>
>
> In terms of what makes PCI difficult, we should leave
> the parity discussion way behind, and talk about
> the irdy/trdy negotiation for every data transfer.
>
> that's what made pci timing hard. and with the transistor
> densities available at the time frame, it was silly trying
> to micro-optimize at that level, as opposed to having 
> fixed size bursts.
>
> The amount of mental energy, translated to dollars, that
> has been wasted, because of that spec decision is staggering.

Hmm, interesting perspective. If we are going to restate things in the
original time frame, though, you have to admit that they did an awesome
job on the signal integrity end.

> A proper spec would have eliminated  the need for AGP/PCI-X..in
> fact the AGP/PCI combination is an embarassing bandaid....How
> do you explain that? ...just by: That's how it goes. There are
> other considerations beyond making a bus available to every 
> mom and pop shop.

Actually, I think it was a proper spec, they did eliminate that need
with 64-bit/66-MHz PCI.

I always interpreted AGP as an intentional swerve back to something Intel
could patent and control, or at least get a head start on, that is, a
business decision to intentionally undercut their own standard, which had
apparently done a little too well. Lots of AGP hardware didn't use the fast
modes, so the practical benefits were small.

> Of course, the garage shop guy wouldn't want fifos, so maybe
> the single data beat negotiation is a good thing, even if you
> can' meet 33mhz timing...(just run at 20mhz I guess...nice if
> you have no performance requirements)

//