Re: Fw: why Master/Target cannot change its mind

[Gérard Roudier <groudier@club-internet.fr>]

Weng,

In my initial response to your proposal, I described a situation that
harms when the master changes its mind after having asserted IRDY#.

The situation corresponds to a master reading to non-prefetchable.

If the target actually reads some non-prefetchable DWORD and cannot
deliver it to the master because the master does not want the data, side
effects will occur without the data being delivered to the software.
Nobody seems to demonstrate that I was wrong here, or may-be nobody
noticed because of my frenchy english :), btw.

About targets that want to change their mind (you seem to focus on that), 
the specs should have to be significantly reworked. What about delayed
transactions, for example ?

Anyway, since some existing masters (?) may be preparing the data when
TRDY# is asserted and IRDY# is deasserted, those masters may have to undo
some stuff and not be able to do so. After all some PCI chip designers may
have taken advantage of the "never change one's mind" PCI clause.

Regards,
  Gérard.

On Mon, 23 Apr 2001, Weng wrote:

> Hi,
> Thank many experts who joined my discusstion about "Why Target cannot change
> its mind", actually after correcting my wrong idea, the topics should be
> "Why Master/Target cannot change their mind".
> 
> One thing is now becoming clear: putting aside the PCI specs consistancy,
> the following claim should have no any problem from technical point of view:
> "when Either Master or Target is inserting wait cycles, NOT FOR LAST
> DATA(FRAME# = '0'), the opposite partner can change its state (IRDY# or
> TRDY#) without any harm if no accompanying STOP# change !!! That's all."
> This assertion will never cause "deadlock" if 16 cycle limit for first data
> cycle and 8 cycle limit are still effective.
> 
> Now I tell you that with above condition, there are a great implemention
> benefit to FPGA chip design:
> If PCI specs were claimed like above, all PCI signals would never have to go
> into AD_O registers(AD_O is output register connected to PCI AD signals, 64
> data signals) with 1 data per clock. That means, it would greatly easy 3 ns
> setup time limit for FPGA design.
> 
> Now with 1 data per clock data flow, my design, and including all designs,
> has IRDY# and TRDY# go to AD_O register. That means, for FPGA design, it's a
> stunning requirement to meet 3 ns setup time. I don't know whether Altera
> chip has such ability to accomodate 3 nds setup time for IRDY# and TRDY#
> with more than 80 fan-out(64 pins of AD_O register).
> 
> Weng
> 
> 
> ----- Original Message -----
> From: Weng <wtx@umem.com>
> To: <pci-sig@znyx.com>
> Sent: Tuesday, April 17, 2001 8:53 AM
> Subject: Re: why Target cannot change its mind
> 
> 
> > Hi Richard,
> > I have been designing PCI core for almost one year. Recently even my
> > design's simulation works excellently well, I found after Altera chip
> > fitting that IRDY# and TRDY# signals are expanded to ReadFIFO if I tried
> to
> > keep 1 data per clock and can properly handle PCI partner's wait cycles at
> > any moment.
> > For Altera chip, it certainly is a mistake, because Altera chip has no
> such
> > capability to meet 3ns setup time with PCI signals' big fanout. So I have
> to
> > redesign a state machine to isolate the two signals to ReadFIFO while
> > keeping 1 data per clock, no matter at any clock wait cycles from PCI
> > partners are inserted.
> >
> > My colleague proposed me an algorithm as follows:
> > Keeping ReadFIFO busy in 1 data per clock mode while doing transfering
> until
> > it sees the IRDY# = '1' as Target or TRDY# = '1' as Master, that is, PCI
> > partner is inserting wait cycle. This way certainly could be used to
> prevent
> > IRDY# & TRDY# signals from entering ReadFIFO, but on the clock PCI partner
> > is inserting wait cycle, IRDY# = '1' as Target or TRDY# = '1' as Master,
> the
> > latest data on PCI bus output would be destroyed by next data from
> ReadFIFO
> > due to the proposed ReadFIFO working mode. The algorithm suggested to
> assert
> > 1 clock wait cycle to restore the damaged data for later transfer. Finally
> I
> > found the algorithm violates PCI specs: both master and target cannot
> change
> > their mind after asserting their data ready signals: TRDY# or IRDY.
> >
> > The algorithm triggers me to think why IRDY# and TRDY# cannot change and
> > want to delay data cycle, for example,  from clock 3 to clock 4 during PCI
> > partner's wait cycles.
> >
> > Finally I resolved the problem perfectly, even much better than the
> > algorithm my colleague proposed to me, but the question is still looming
> > over my mind.
> >
> > Weng Tianxiang
> >
> > wtx@umem.com
> > wengtianxiang@yahoo.com
> >
> > Micro Memory Inc.
> > 9540 Vassar Avenue
> > Chartsworth, CA 91311
> > Tel: 818-998-0070
> > Fax: 818-998-4459
> >
> > ----- Original Message -----
> > From: Richard Iachetta <iachetta@us.ibm.com>
> > To: <pci-sig@znyx.com>
> > Sent: Monday, April 16, 2001 1:14 PM
> > Subject: Re: why Target cannot change its mind
> >
> >
> > > >I have to say that I have never backed out from my original view:
> > > >"when Either Master or Target is inserting wait cycles, NOT FOR LAST
> DATA
> > > >(FRAME# = '0'), the opposite partner can change its state (IRDY# or
> > TRDY#)
> > > >without any harm if no accompanying STOP# change !!! That's all."
> > >
> > > Weng,
> > >
> > > Can you explain why a target would ever want to assert its TRDY# and
> then
> > > later change its mind before the data was transferred?  What benefit
> could
> > > be gained by having the bus support that?
> > >
> > > Rich Iachetta
> > > IBM Microelectronics Division -- Austin
> > > World Wide Field Design Center
> > > Phone: 512-838-6305   Tie Line: 678-6305
> > >
> > >
> >
> 
>