Re: Fw: why Master/Target cannot change its mind

["Weng" <wtx@umem.com>]

Hi Gerard,
My condition "NOT FOR LAST DATA (FRAME# = '0')" eliminates any
non-prefetchable area problem for Master/Target.

"when Either Master or Target is inserting wait cycles, NOT FOR LAST
DATA(FRAME# = '0'), the opposite partner can change its state (IRDY# or
TRDY#) without any harm if no accompanying STOP# change !!! That's all."
This assertion will never cause "deadlock" if 16 cycle limit for first data
cycle and 8 cycle limit are still effective.

In another words, my suggestion that Master/Target can change their mind if
it is not for last data. It is purely for FPGA implementation reason.

I know there is no any chance for me to change PCI specs, the discussion is
only for interested people in THEORY, not for PRACTICE.

Weng


----- Original Message -----
From: Wen-King Su <wen-king@myri.com>
To: <pci-sig@znyx.com>
Sent: Monday, April 23, 2001 1:14 PM
Subject: Re: Fw: why Master/Target cannot change its mind


> >From: =?ISO-8859-1?Q?G=E9rard_Roudier?= <groudier@club-internet.fr>
> >
> >Weng,
> >
> >In my initial response to your proposal, I described a situation that
> >harms when the master changes its mind after having asserted IRDY#.
> >
> >The situation corresponds to a master reading to non-prefetchable.
>
> Prefetchability and side-effect are two different things.  A read to a
> temperature sensor is non-prefetchable, but it does not have to have
> any side effects.  What you are referring to here is read with side
> effects.
>
> I think what weng described is a bit incomplete.  In particular, I
> would like to know what happens to FRAME# when IRDY# changes.  While
> not endorsing weng's proposal, I would say with the right FRAME#
> behavior, I see no more problems regarding read side-effects as
> compared to regular PCI.  Remember, target cannot wait for IRDY#
> to be asserted as a pre-condition to its asserting TRDY#.
>
>