CACHE ON PCI SIDE

["SUSHANT S RANADE" <ssr@myw.ltindia.com>]

hi all,
i am designing a pci2.1 based real-time image graberar card,
struck with some cache related probs.

1.
from pci2.1 specs i got some information that pci based device can impliment cache memory on the device. what it means?
as accessing any memory of the pci device by other masters, it need to map it in memory or io space. that means it will get some physical address. 
but, also the specs said that for cache related cycles the byte enables should not be considered. why? if Icache is having the physical address, i can use normal read/write cycles with valid byte enables.

or is it so, that the Icache should be considered just as  Internal mamory, which meets the timing (access time,..)parameters of local(host side) cache?

2.
what actuallu the cache-line-size register in header config type 0 indicates? & for who?
is it indicate the cache size of pci based device's Internal cache or the local (host side) cache memory?

3. 
why the main cache#1 on host side(processor inbuilt) is limited max upto 1MB. is it only for the backward compatiblity? or any real technical problem?

thanking in advance,

regards,

RANADE SUSHANT
ADesign Engg.
EmSyS, L&T,
Mysore, INDIA