Re: Incorrect Target Termination?

["Weng" <wtx@umem.com>]

Hi,
Both Master and Target are wrong.

It should be look like this:
 1 2 3 4 5 6 clk
110000001111 frame
111100000111 irdy        <--- Master error here, corrected
111111000111 devsel    <--- Target error here, corrected
111111000111 stop
111111111111 trdy

1. Master error:
Master should deassert irdy after last data cycle: frame: 1, irdy: 0, stop
0.

2. Target error:
Target cannot deassert devsel until last data cycle.

Weng Tianxiang

wtx@umem.com
wengtianxiang@yahoo.com

Micro Memory Inc.
9540 Vassar Avenue
Chartsworth, CA 91311
Tel: 818-998-0070
Fax: 818-998-4459

----- Original Message -----
From: Konstantin Neskovic <bs844@freenet.carleton.ca>
To: <pci-sig@znyx.com>
Cc: <bs844@freenet.carleton.ca>
Sent: Friday, May 04, 2001 5:48 AM
Subject: Incorrect Target Termination?


> Hi,
>
> Is it OK for a PCI compliant target to issue a target
> abort as shown below.
>
>
>  1 2 3 4 5 6 clk
> 110000001111 frame
> 111100000011 irdy
> 111111001111 devsel
> 111111000011 stop
> 111111111111 trdy
>
> Regards and Thanks in Advance,
> Konstantin
>
>