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Re: Incorrect Target Termination?
On Fri, 4 May 2001, Konstantin Neskovic wrote:
> Hi Weng,
> Thanks for a prompt respnse. Please note that in enclosed
> waveforms one clock cyle is represented with two digits.
> 1 2 3 4 5 6 clk
> 110000001111 frame
> 111100000011 irdy
> 111111001111 devsel
> 111111000011 stop
> 111111111111 trdy
> I am confused by the fact this target issues a Target disconnect on
> cycle 4 and then follows with a Target Abort on cycle 5.
> At least, that's how I read it ;-).
You should read it as a PCI protocol error, in my opinion. :-)
The target starts a termination with retry on clock 4, but should wait for
the transaction to complete (clock 6) prior to deasserting DEVSEL.
A target abort requires DEVSEL to be deasserted and STOP to be asserted at
the same time. This does not happen on the waveforms above.
> Regards and Thanks again,