RE: Read Speed

["Olaf Birkeland" <Olaf.Birkeland@fast.no>]

Hi,

We've tried this as well (although we of course use DMA for real application
SW ;-), but with better success. In Linux, we added a MTRR by the command:

echo "base=0xd9000000 size=0x400000 type=write-back">/proc/mtrr

This setting is of course dependent on where you card is mapped, and whether
your memory is prefetchable or not. I our case, we reached almost 50 MB/s
reading from the CPU with this setup (8 dword bursts), including some added
latency as the target device is behind a PCI bridge. We used memcpy() for
reading the memory.

MTRR is only available on PentiumII and upwards. Test system had 733 MHz
PIII, i815E chipset. But again: Memory transfer by CPU reads are not
advisable......

Regards,
- Olaf Birkeland

> -----Original Message-----
> From: adavid@pcru00.cern.ch [mailto:adavid@pcru00.cern.ch]On Behalf Of
> André David
> Sent: Thursday, April 05, 2001 17:19
> To: pci-sig@znyx.com
> Subject: Read Speed
>
>
> Hi!
>
> I am working on a group developing a PCI board for data acquisition.
> Since our priority is getting it running, busmastering capabilities for
> such things as DMA to the host memory are not on the front line of
> development.
>
> Now, since I'm the guy behing the device driver, I have done some
> benchmarking with a simple device driver (in Linux, of course) using a
> standar PCI VGA adapter.
> This "driver" just uses the memcpy() transfer some data between the main
> memory and the board's framebuffer.
>
> I have tried three different processor/chipset combinations and the
> results I get, are:
>
> (results after BIOS and MTRR parameters tweaking)
>
>                                              Reading (Mbyte/s)
> Writing(Mbyte/s)
> Intel 440FX (PII@233)                7.03
> 36.16
> Intel 440BX (2*PII@400)            8.62                        102.4
> VIA KT133 (Athlon@900)            7.46                        119.6
>
> Now this points to a pattern in which the north bridge seems unable to
> read with a reasonable speed from the board. I know writing is always
> easier than reading (from the specs a single data phase read is slower
> than a single data phase write (4 clock cycles vs. 3)).
>
> The north bridge behaviour is inadmissible even if we assume that all
> the reads are single data phase reads (4 clock cycles), with even medium
> devsel (1 more clock cycle lost) and a wait-state from the VGA board
> (another clock sycle lost), because this would give a total of 6 clock
> cycles, or 22Mb/s total bandwidth.
>
> So my questions are:
>
> - Since it looks that north bridges have always been like this, has
> anyone found one that is not?
> - Is it admissible (logical) that the north bridge is like this?
> - Since I have only talked about commodity PC's, could there be
> something on the industrial market that does not suffer from this
> apparent "feature"?
>
> Thanks in advance for all comments,
>
> Andre David
>