PCI-IDE Bridge/Controller Chips

["John Weil" <ra8636@email.sps.mot.com>]

All:


When writing to the data register in I/O space, what will happen if all
four PCI byte enables are asserted?

Will the bridge chip allow this access? Or will it perform a target
abort?

The ATA data register is 16 bits, but we are unsure how the PCI/ATA
bridges interface to the ATA standard.
We have seen specs for Intel's south bridges, which will accept 32 bit
accesses and split them into the 16 bit transfers, but we are wondering
how other PCI/ATA bridges handle this conversion.



Thanks
John Weil
Ryan McDaniel
Systems Engineering