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Re: PCI-IDE Bridge/Controller Chips
Every PCI IDE controller I've seen puts a small FIFO behind the data port
and buffers the single 32-bit write into the two 16-bit writes required on
the IDE interface. Turns out that the buffer doesn't have to be deeper than
4 bytes since the x86 I/O instructions take a large number of clocks per
I don't know that its a spec'ed requirement (i.e., I don't know that you
can depend on it), but its probably a fairly strong standard due to market
(chipset grunt in a former incarnation)
John Weil wrote:
> When writing to the data register in I/O space, what will happen if all
> four PCI byte enables are asserted?
> Will the bridge chip allow this access? Or will it perform a target
> The ATA data register is 16 bits, but we are unsure how the PCI/ATA
> bridges interface to the ATA standard.
> We have seen specs for Intel's south bridges, which will accept 32 bit
> accesses and split them into the 16 bit transfers, but we are wondering
> how other PCI/ATA bridges handle this conversion.
> John Weil
> Ryan McDaniel
> Systems Engineering
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