Re: PCI-IDE Bridge/Controller Chips

["Frank Story" <frank.story@acoustictech.com>]

Hi John,

Every PCI IDE controller I've seen puts a small FIFO behind the data port
and buffers the single 32-bit write into the two 16-bit writes required on
the IDE interface. Turns out that the buffer doesn't have to be deeper than
4 bytes since the x86 I/O instructions take a large number of clocks per
transfer.

I don't know that its a spec'ed requirement (i.e., I don't know that you
can depend on it), but its probably a fairly strong standard due to market
pressures.

Frank
(chipset grunt in a former incarnation)


John Weil wrote:

> All:
>
> When writing to the data register in I/O space, what will happen if all
> four PCI byte enables are asserted?
>
> Will the bridge chip allow this access? Or will it perform a target
> abort?
>
> The ATA data register is 16 bits, but we are unsure how the PCI/ATA
> bridges interface to the ATA standard.
> We have seen specs for Intel's south bridges, which will accept 32 bit
> accesses and split them into the 16 bit transfers, but we are wondering
> how other PCI/ATA bridges handle this conversion.
>
> Thanks
> John Weil
> Ryan McDaniel
> Systems Engineering

--
Frank Story
Acoustic Technologies, Inc.                   Ph. (480) 456-3641
1921 S. Alma School Road, Suite 313           Fax (480) 456-0105
Mesa, AZ 85210                      frank.story@acoustictech.com