PCI-X 1.0 Specifications on Memory BARs

["Muthrasanallur, Sridhar" <sridhar.muthrasanallur@intel.com>]

I'am trying to get clarity on a PCI-X Base Address Register Issue. 

PCI-X requires that "all" memory BARs (including memory-mapped I/O BAR) in a
PCI-X device be 64-bit addressable. And the prefetchable bit in the BAR is
to be set if reads to the memory region associated with the BAR has no read
side-effects and writes to that region are byte-mergable. This means
memory-mapped I/O regions which could have read side-effects must not set
this bit and be 64-bit addressable. Now, if a PCI-X device with a
memory-mapped I/O (with read side-effectc) sits behind a P2P bridge then
this region has to be always mapped below 4GB by BIOS (because of the way
memory-mapped I/O regions are handled through a P2P bridge), in which case
the requirement for the memory-mapped I/O BAR to be 64-bit addressable is
not needed. It could be 32-bit addressable also. This model for BARs also
requires that the enumeration BIOS be smart enough to realise that even
though a memory-mapped I/O BAR (with prefetch bit turned off) requests
itself to be placed anywhere in the 64-bit space, the BIOS always has to map
it below 4GB if the BAR resides behind a P2P bridge.

Any comments/clarifications on this specification issue from PCI-X
system/BIOS designers?