Bridge throughput problems at 64bit/66Mhz

[Christer Olsson <Christer.Olsson@emw.ericsson.se>]

Hi,

Has anyone experienced problems with a bridge device 
running at different bandwidths at each side ?

We have a CompactPCI design that incorporates an Intel 21154
PCI bridge connected between the backplane bus and our
local bus which hosts several PCI devices. One of the PCI
devices is a bandwidth consuming Gigabit Ethernet chip.
The local bus is set up to 64bit/33Mhz. 

When the bridge primary bus (backplane) interface runs 
at full speed, i.e. 64bit/66Mhz, the Gigabit Ethernet
chip reports REDUCED data packet throughput (~100 MB/s)
compared to when the primary bus interface is set to either
32bit/66Mhz OR 64bit/33MHz (~125 MB/s). The increased
available bandwidth on the primary side does in fact LOWER
the data throughput!

One theory is that the different bandwidths at the bridge
interface causes this problem (for example by a mismatch
in FIFO fill rates).

regards

Christer Olsson, Ericsson