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RE: Bridge throughput problems at 64bit/66Mhz
Your suspicion is correct. If the bandwidth on the bus providing the data is
lower than the bandwidth on the bus receiving the data, the bridge will not
operate in "flow through" mode, but instead, it will operate in store and
forward mode. This is explained in the bridge datasheet section 4.9,
"Transaction Flow Through".
In your case, since the initiator bus runs at a lower bandwidth than the
target bus, write DMA operations that use the PCI Write and Invalidate
command will end up (after the first burst that fills the FIFO) moving only
one cache line at a time into the bridge and get disconnected. The bridge
will not start the operation on the target bus until the initiator bus is
disconnected. Subsequent accesses to continue the DMA operation will get
"retries" until there is enough room in the bridge FIFO for one cache line.
Worse yet, if other PCI devices get to the bridge in between, the Ethernet
agent trying to do the DMA operation may get lots of retries.
We have a case in which the secondary bus is 64/33 while the primary bus is
64/66. We have 4 agents behind the bridge. A similar effect occurs. As the
load presented by the 4 agents behind the bridge increases the throughput
begins to flatten out. The overall throughput is less than if the primary
bus is set for 64/33 operation.
From: Christer Olsson [mailto:Christer.Olsson@emw.ericsson.se]
Sent: Thursday, May 10, 2001 5:57 AM
Subject: Bridge throughput problems at 64bit/66Mhz
Has anyone experienced problems with a bridge device
running at different bandwidths at each side ?
We have a CompactPCI design that incorporates an Intel 21154
PCI bridge connected between the backplane bus and our
local bus which hosts several PCI devices. One of the PCI
devices is a bandwidth consuming Gigabit Ethernet chip.
The local bus is set up to 64bit/33Mhz.
When the bridge primary bus (backplane) interface runs
at full speed, i.e. 64bit/66Mhz, the Gigabit Ethernet
chip reports REDUCED data packet throughput (~100 MB/s)
compared to when the primary bus interface is set to either
32bit/66Mhz OR 64bit/33MHz (~125 MB/s). The increased
available bandwidth on the primary side does in fact LOWER
the data throughput!
One theory is that the different bandwidths at the bridge
interface causes this problem (for example by a mismatch
in FIFO fill rates).
Christer Olsson, Ericsson