How to handle a requirement for dual PCI FPGA configuration serial bitstreams.

["Jeffrey Journey" <jjourney@us.ibm.com>]

Hello PCI reflector readers,

I am designing a 32 bit 33MHz PCI universal card. The PCI interface FPGA
that I am using requires two different download serial bit streams, one to
support the 3.3 volt PCI signaling environment and one to support the 5.0
volt PCI signaling environment. I would appreciate some feedback from
anyone who has some experience with this scenario. What I am considering is
having two eeproms installed on my card and using the Vi/o connector signal
(in conjunction with a voltage comparator) to select between the two
eeproms for configuring the FPGA at power-up. I would be interested in
hearing from anyone who has had this same design challenge and the solution
that you implemented to solve it.

Thanks,
Jeff Journey