RE: PCI clock jitter

["Ingraham, Andrew" <Andrew.Ingraham@compaq.com>]

I received the following reply from Martijn Emons
(martijn.j.emons@philips.com) who requested that I forward it to the pci-sig
maillist, because he doesn't have access to the account needed to submit it
to the reflector himself.

Andy
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Martijn J Emons
05/28/2001 03:17 AM
To:	Andrew.Ingraham@compaq.com@SMTP
cc:	pci-sig@znyx.com@SMTP 
Subject:	RE: PCI clock jitter  
Classification:	Unclassified



Hi all,

There are two types of 'jitter':
1. edge-to-ege jitter, this is specified by the spec's that Andrew was
pointing to, see below.
2. long-term stability .. also know as  'absolute frequency tolernance' or
'long-term jitter'.
     (caused by temperature-impact etc.).
On the point number two:
There is a table in the PCI-spec that specifies the 'tolerance' of the CLK
signal, specified in a unit called 'ppm'.
This is specified near the table that Andrew was pointing to ('Clock and
reset'  .... something ... I think).

This figure can be used to determine long-term jitter-requirements:
-using: 66.00 MHz x figure_in_table x 10e-6 = ... MHz or in time-domain:
- using (1/66.00 MHz) x figure_in_table x 10e-6 = ... micro-seconds.

Note, that the jitter-spec that you will calculate is not very
'high-quality' when compared with what is needed in
telecom-systems etc. .. but that's obvious, considering that PCI is targeted
as medium on a PCB, hence
do NOT to use (the) PCI(-clock) as reference for any other transmission
protocol than PCI itself.

Kind regards,
Martijn Emons
Arcobel ASIC design Centre. bv
The Netherlands
+31-73-6460100





Andrew.Ingraham@compaq.com on 05/24/2001 02:59:00 PM
To:	pci-sig@znyx.com@SMTP
cc:	 
Subject:	RE: PCI clock jitter
Classification:	


> Does anyone know if a specification on the allowed jitter of the CLK
> signal
> exist ?

For 33 MHz PCI, there is no limit on CLK jitter.  It can be almost infinite,
just as long as the CLK meets the minimum clock cycle time (and pulsewidth)
for every cycle.

application/ms-tnef