Re: How to handle a requirement for dual PCI FPGA configuration serial bit streams.

[Eric Crabill <crabill@xilinx.com> (by way of Daniel Weaver <dan.weaver@znyx.com>)]

Hi Jeff,

I can offer you a solution, however it may not be the
most cost effective one.  Depending on your requirements,
it may not be appropriate.

I suggest using the TL712 differential comparator from
Texas Instruments.  This comparator has complementary
outputs and an output enable.

You tie Vio to one of the comparator inputs, and then
create a reference voltage around 4.1 volts using a
resistive divider for the other comparator input.  The
comparator will then be detecting which bus voltage
is in use.

With the complementary outputs, interfacing to the SPROM
devices is easy; each output of the comparator goes to a
different SPROM output enable pin so that only one SPROM
is enabled based on the bus voltage.  This assumes you
have the enable of the comparator permanently asserted.

You tie the data outputs of the SPROMs together, which is
okay since only one will actively drive at any time.

What is really nice about this comparator is its output
enable function.  If you put pullups on its outputs, and
have the enable run to a jumper, you can disable both
SPROMs at the same time.  If you then take the same
output enable signal from the jumper and run it to the
FPGA to select between slave serial and master serial
modes (on the M0, M1, and M2 pins) you can have one
jumper which disables the SPROMs and puts the FPGA in
slave serial mode -- this allows you to easily put on
another header to connect a download cable (Xilinx
Parallel Cable or MultiLINX) for debugging purposes.

I think it is a great solution.  It will cost you:

2 SPROMs (3.3v/5.0v bitstream storage)
1 3x1 header (master/slave mode select)
2 resistors (generate ~4.1v reference)
1 TL712 (comparator)
1 9x1 header (for debug cable)

Hope that helps,
Eric Crabill

> I am designing a 32 bit 33MHz PCI universal card. The PCI interface FPGA
> that I am using requires two different download serial bit streams, one to
> support the 3.3 volt PCI signaling environment and one to support the 5.0
> volt PCI signaling environment. I would appreciate some feedback from
> anyone who has some experience with this scenario. What I am considering is
> having two eeproms installed on my card and using the Vi/o connector signal
> (in conjunction with a voltage comparator) to select between the two
> eeproms for configuring the FPGA at power-up. I would be interested in
> hearing from anyone who has had this same design challenge and the solution
> that you implemented to solve it.