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Re: Compaq PCI-X Verilog core
Its good that Compaq is offering a free core. BUT you need to know few things
before you really use it.
If you are familiar at PCI and PCI-X, then you must be already knowing these
1. Does it support PCI-X Rev 1.0a
2. Does it support PCI Rev 2.2
3. If operating at 66 MHz PCI, can you really use this core (setup for
control pins is just 3 nsec). This is one
of the big issues that "everyone" faces for 66 MHz PCI.
4. You cannot expect good support for the RTL (my belief). If a bug is
found, it does not mean that compaq
is going to release the fix in next release or quarter. Or else if you
fix the bug, how do you make sure that
you have not broken PCI / PCI-X functionality in doing so.
5. Adding PCI back to back quite a critical change. It also means changing
the main PCI control pin
SM's. And if you do so yourself, you will have to make sure that the
changes does not break any
of the normal PCI functionality. And to test PCI functionality
(PCI Core) lots of testing needs to be done.
Normally when you buy a core, you know that the core is fully tested
and you can always tell them to run
their test suite on your modified code.
Now if you change it locally, most probably nobody is going to run the
whole PCI test suite
to verify the PCI core is still good. And building a test suite for
PCI locally is a small project itself.
Also it will affect the timing critical path of 3 nsec. So watch out.
6. Just try to call them find it for yourself how good their support for
RTL is going to be.
Any ways, All the best.
Brent Barr wrote:
> The current Compaq X-Caliber Megacell Initiator does not support fast
> back-to-back PCI Transactions when in PCI 2.2 mode. This was the main mode
> that I wanted to use. Has anyone tried to modify the code to support this
> case? Was it easy/impossible?
> Brent Barr
> Senior Design Engineer
> F5 Networks
> 1322 N. Whitman Lane
> Liberty Lake, WA 99019
> DID: 509-343-3502
> FAX: 509-343-3501