RE: Compaq PCI-X Verilog core

[Brent Barr <b.barr@f5.com>]

Thanks for your advise-  You bring up good points. I will look in to them
further.  Unfortunately, Synopsys told me that I have to use their Design
Compiler if I want to use their core, but we are a Cadence Ambit house so I
don't have access to DC, hence I cannot use their core, even though we have
it. 
Both DCM and Synopsys claim to have the full test suite...  since we will be
the only device on the bus, and only talking to one chipset, it should not
be too hard to verify that all the cases we actually use sim fine. 

I would be perfectly happy purchasing a core, if it could be had for a price
within my budget. Unfortunately, as we have two PCI busses in our chip, the
cost of two cores ranges from $70k to $200k, which is far beyond what I can
pay. The original plan was to use the "free" core that our silicon vendor
supplies, but we just learned that it is only 2.1 compliant. Since I have to
use a different core, I am trying to take this opportunity to upgrade to
PCI-X....  but I can't spend much for it.

I am concerned about TANSTAFL, but at this point, I think the risk is
acceptable.

Thanks again for your advise-  I'll let you know more in two months.  :)


Brent



(TANSTAFL= There Aint No Such Thing As a Free Lunch )


-----Original Message-----
From: Amit Shah [mailto:amits@agere.com]
Sent: Wednesday, June 06, 2001 4:01 PM
To: Brent Barr
Cc: 'pci-sig@znyx.com'
Subject: Re: Compaq PCI-X Verilog core


Brent,

1.  Getting a internal operation at 120 MHz is easy. But What I meant by 66
MHz
timing being very difficult
     is meeting the setup time of 3 nsec and a clk to Q (for outputs) of 6
nsec. I have not met a single engr
     who has worked on PCI 66 MHz and having no issues meeting these
timings.
This is mainly
     because the PCI control signals are not flopped as in PCI-X. So you
will
see that the PCI input
     signal will go through n stages of gates before hitting a flop. Now if
the
number n is say more than 10,
     then as soon as you try to place the CORE on silicon, you will lots of
timing violations. There are some
      innovative ways to deal with a bad spec like PCI (as far as electrical
timings is concerned), but
      usually its a pain. So check your synthesis results for the setup time
results that you have got and
      how many levels of logic you have before a flop. 3nsec setup is a
killer.

2.   DCM and Synopsys do offer test suite but I am not sure whether they
offer
the whole
      PCI compliance test suite or not. Also this PCI compliance test suite
is
not "only" the PCI
      compliance tests listed on pcisig. Its a very big test plan to check
the
PCI core behavior
      in all possible PCI conditions. (I have worked on PCI core's (design)
and
I know the how
      big the test plans are). So if you get this test plan's in form of
code
from these companies then
      its great. But as far a I know they give you the BFM's and trackers
and
maybe some basic
      PCI test plan.
3.   I have also worked with PCI Core from Synopsys. Its free as a netlist
and
you pay some small
       amt if you want the RTL. And its available from quite a time and I
know
that lots of synopsys customers
       use this core as its very cheap. But still we found 2 bugs in one of
our  presentchips (silicon) in which
      we were using this core. Also we had found quite a few bugs during
testing.
     So assuming that the Compaq core is available from past one year, means
it
will have negligible bugs
      may not be good. Also I am not sure how many companies are really
using
that core and testing it. This
     does not mean that you should not use Compaq's core, but you should be
very clear of how are
     are you going to test your modified code.

This is just a word of caution. These are few things someone should consider
before making any decision.

Amit



Brent Barr wrote:

> 1- But of course.
> 2- ditto, with a short list of non-supported features, the biggest one
being
> no support for back-to-back transfers.
> 3- I just simmed it out running at 120 Mhz (very tight in our process), I
> don't expect a problem at 66 Mhz.
> 4- No support is expected.  However, I do have the source code, which is
> much easier to debug than an encrypted netlist.
> 5- True-  But that is standard with any changes. If you cannot test the
> changes you made, don't make them. We are going to purchase the DCM or
> Synopsys test suite anyway, if they do not satisfactorily test the core,
> that is a different problem.
> 6- Again, no support is expected. However the code has been available for
> over a year. I would like to believe that if there were major problems
they
> would have fixed them by now, or I would have heard of them from this list
> at least.
>
> Thanks for the comments-
>
> Brent Barr
> Senior Design Engineer
> F5 Networks
>
> -----Original Message-----
> From: Amit Shah [mailto:amits@agere.com]
> Sent: Wednesday, June 06, 2001 3:17 PM
> To: Brent Barr
> Cc: 'pci-sig@znyx.com'
> Subject: Re: Compaq PCI-X Verilog core
>
> Brent,
>
> Its good that Compaq is offering a free core. BUT you need to know few
> things
> before you really use it.
> If you are familiar at PCI and PCI-X, then you must be already knowing
these
> issues.
>
> 1.  Does it support PCI-X Rev 1.0a
> 2.  Does it support PCI Rev 2.2
> 3.  If operating at 66 MHz PCI, can you really use this core (setup for
> control pins is just 3 nsec). This is one
>       of the big issues that "everyone" faces for 66 MHz PCI.
> 4.  You cannot expect good support for the RTL (my belief). If a bug is
> found, it does not mean that compaq
>       is going to release the fix in next release or quarter. Or else if
you
> fix the bug, how do you make sure that
>       you have not broken PCI / PCI-X functionality in doing so.
> 5.   Adding PCI back to back quite a critical change. It also means
changing
> the main PCI control pin
>        SM's. And if you do so yourself, you will have to make sure that
the
> changes does not break any
>        of the normal PCI functionality. And to test PCI functionality
> (PCI Core) lots of testing needs to be done.
>        Normally when you buy a core, you know that the core is fully
tested
> and you can always tell them to run
>        their test suite on your modified code.
>        Now if you change it locally, most probably nobody is going to run
> the
> whole PCI test suite
>        to verify the PCI core is still good. And building a test suite for
> PCI locally is a small project itself.
>        Also it will affect the timing critical path of 3 nsec. So watch
out.
> 6.    Just try to call them find it for yourself how good their support
for
> RTL is going to be.
>
> Any ways, All the best.
>
> Amit Shah
> Design Engr
> Agere Systems
> Austin
>
> Brent Barr wrote:
>
> > The current Compaq X-Caliber Megacell Initiator does not support fast
> > back-to-back PCI Transactions when in PCI 2.2 mode. This was the main
mode
> > that I wanted to use. Has anyone tried to modify the code to support
this
> > case?  Was it easy/impossible?
> >
> > Thanks-
> >
> > Brent Barr
> > Senior Design Engineer
> > F5 Networks
> > 1322 N. Whitman Lane
> > Liberty Lake, WA  99019
> > DID: 509-343-3502
> > FAX: 509-343-3501
> > www.f5.com