32 bit PCI, BAR -> FIFO.

["Xavi Neuri" <xcano@neuricam.com>]

Hi,

Thanks to everybody, your explanations are being a source of real
knowledege.
The next one. My PCI device has to work only to read and write two
independent FIFOs, which I've planned to assign a BAR for each one, to
address it. So I know the
max block to transfer (the FIFO depth) and I wouldn't need to decode any
possible address, only the base, and use it as a device select for the
specific FIFO. Is this coherent or am I missing something important?

Thank you

Xavier Cano