Re: How to generate 64-bit transfer?

["Prateek Sharma" <prateeks@us.ibm.com>]

Hi,

I have seen a couple of PCI Master implementations where they have a logic
that generates 32-bit read transactions instead of one 64-bit read
transaction in order to get around the problem of re-initiating read cycle
in case target turns out to be 32-bit (you will come to know about it when
your FRAME# has already gone high), to get upper 32-bit data. This is just
a performance issue. Master can get data faster in a 32-bit burst of 2 data
phases than re-initiating the cycle.

I guess this might be the case with this chipset also. You can generate
64-bit reads if you try to read more than 8 bytes.

Correct me If I am wrong.

regards,
Prateek Sharma





Taliaferro Smith <TollyS@Lewiz.com> on 06/11/2001 04:51:31 AM

To:   pci-sig@znyx.com
cc:
Subject:  How to generate 64-bit transfer?



I have an STL2 motherboard with PIII and the ServerWorks ServerSet III
LE Chipset containing
the NB6635 North Bridge 3.0 LE.

I'm attempting to read a 64 bit register from a 64/66 PCI Card in a
single 64-bit transfer.
I used the mmx  movq instruction.
I'm getting two 32-bit reads in a single burst.
I never see Req64 go low.
I also tried the FILD floating point instruction.

What am I doing wrong?
Does this chipset support 64-bit transfers, or only with the card as
master?

Thanks,

Tolly Smith
LeWiz Communicaions
TollyS@Lewiz.com