RE: PCI-X Bus loading in Pf

[Brent Barr <b.barr@f5.com>]

Our vendor does have a standard PCI buffer cell, but knows nothing about
PCI-X. I do not think I can convince them to generate a PCI-X buffer cell in
time. Their plan for supporting PCI-X is "sometime later this year", which
would probably translate to 3rd quarter 2002.  It is far too late for us to
change vendors at this time. Our volumes will be low, and not many companies
want to even bother with us. If all else fails, I'll have to use the
standard PCI buffers and hope they work in our embedded point-to-point PCI-X
application.  Since there is only our chip and the host bridge on the bus,
with no connectors, the signal paths are very simple.

I will try to get them to do the PCI-X cells, but don't hold out much hope.
The original plan was to use PCI 2.2, so that is what they were expecting.
Getting them to do more design work for little to no charge would not be
easy. :)


Thanks for the clarification on the lumped capacitance. I agree with what
you are saying. I am mostly looking for ball park numbers to help validate
the I/O cells that I will have to use. The only number I question is the 3pf
/ inch for traces. My board guy says that for our 12 layer impedance
controlled boards, it is much less than 1 pf / inch. His number was about
1pf for the entire 3 inch trace.


New question-  Is it acceptable for me to send the vendor the PCI-X specs,
or are they required to join the SIG to get them?  I was thinking of faxing
just the I/O pages to the engineer who is doing the work-  That would be far
easier then him convincing his management to release funds, cutting a PO,
etc....


Thank you for you help!


Brent Barr


>  -----Original Message-----
> From: 	Ingraham, Andrew [mailto:Andrew.Ingraham@compaq.com] 
> Sent:	Thursday, June 14, 2001 7:44 AM
> To:	pci-sig@znyx.com
> Subject:	RE: PCI-X Bus loading in Pf
> 
> I would be wary of using a buffer designed on the basis of only a simple
> XpF load, especially at PCI-X speeds.  Real loads aren't like that, and it
> seems inappropriate to define a buffer on the basis of such a load when
> pushing 133MHz switching speeds.
> 
> I might also be rather wary of an ASIC vendor that refuses to make a PCI-X
> buffer (one that meets the PCI-X specs).  You might consider changing
> vendors to one that supports PCI-X, thereby sending a message to the first
> vendor that they are out-of-step.
> 
> Both PCI and PCI-X define minimum and maximum drive strengths (in the form
> of V/I curves), slew rates, and timing specs into specified test loads.
> Your ASIC vendor does not need to "perfectly match" the curves!  The
> curves are limits.  All they need to do is fall within the curves.  While
> it is more difficult to do this for PCI-X than it was for PCI, because the
> PCI-X curves are closer together, that's what you pay in order to get the
> higher speeds.
> 
> 
> What is a realistic capacitive load to assume for a PCI-X bus?  Since at
> 133
> MHz it is only a single slot, my guess is 8pf for the other end, 4pf for
> the
> slot, plus the 8pf at the source puts me at about 20pf.  At 100Mhz with
> two
> slots I get about 32pf.
> 
> If you really want round numbers ... each PCI-X IC can have an input
> capacitance at its pins of up to 8pF.  10pF for a PCI IC.  Remember that
> you can plug a PCI card into a PCI-X slot, or vice-versa, but of course it
> won't be running at 133MHz.
> 
> I didn't think it was customary to count the capacitance of the driving
> IC, when you sum the total load capacitance driven by an output buffer.
> 
> I have seen values of around 2-3pF for the PCI/PCI-X connector itself.
> 
> Traces are about 3pF/inch.  They might be as much as 2.75 inches long
> (about 8pF) on each PCI-X card.  Figure about an inch between each slot on
> the motherboard, plus unknown lengths to the slots from the host bridge IC
> plus any other PCI/PCI-X devices on the motherboard.  So a 4-slot system
> might have a total capacitance approaching 100pF.  For a 1-slot bus, maybe
> 20-35pF.  Two slots, 35-55pF.  Maybe more, maybe less.
> 
> But one shouldn't design their buffers based on the total lumped
> capacitance.  If a buffer has a 1ns rise time, anything that is more than
> three inches away, isn't even "seen" by the buffer until it has already
> finished slewing.  You need to treat these nets as distributed lines with
> occasional lumped loads hung on them.
> 
> Neither PCI nor PCI-X limits you to four slots.  By trading off clock
> speed, for example, a system designer could build a box with a dozen slots
> on one bus.  How would your ASIC vendor handle the fact that your IC might
> drive anywhere from one to a dozen loads?  Don't think of the loads as a
> single lumped capacitance.
> 
> Regards,
> Andy
>