RE: PCI-X Bus loading in Pf

["Ingraham, Andrew" <Andrew.Ingraham@compaq.com>]

I would be wary of using a buffer designed on the basis of only a simple XpF
load, especially at PCI-X speeds.  Real loads aren't like that, and it seems
inappropriate to define a buffer on the basis of such a load when pushing
133MHz switching speeds.

I might also be rather wary of an ASIC vendor that refuses to make a PCI-X
buffer (one that meets the PCI-X specs).  You might consider changing
vendors to one that supports PCI-X, thereby sending a message to the first
vendor that they are out-of-step.

Both PCI and PCI-X define minimum and maximum drive strengths (in the form
of V/I curves), slew rates, and timing specs into specified test loads.
Your ASIC vendor does not need to "perfectly match" the curves!  The curves
are limits.  All they need to do is fall within the curves.  While it is
more difficult to do this for PCI-X than it was for PCI, because the PCI-X
curves are closer together, that's what you pay in order to get the higher
speeds.


> What is a realistic capacitive load to assume for a PCI-X bus?  Since at
> 133
> MHz it is only a single slot, my guess is 8pf for the other end, 4pf for
> the
> slot, plus the 8pf at the source puts me at about 20pf.  At 100Mhz with
> two
> slots I get about 32pf.
> 
If you really want round numbers ... each PCI-X IC can have an input
capacitance at its pins of up to 8pF.  10pF for a PCI IC.  Remember that you
can plug a PCI card into a PCI-X slot, or vice-versa, but of course it won't
be running at 133MHz.

I didn't think it was customary to count the capacitance of the driving IC,
when you sum the total load capacitance driven by an output buffer.

I have seen values of around 2-3pF for the PCI/PCI-X connector itself.

Traces are about 3pF/inch.  They might be as much as 2.75 inches long (about
8pF) on each PCI-X card.  Figure about an inch between each slot on the
motherboard, plus unknown lengths to the slots from the host bridge IC plus
any other PCI/PCI-X devices on the motherboard.  So a 4-slot system might
have a total capacitance approaching 100pF.  For a 1-slot bus, maybe
20-35pF.  Two slots, 35-55pF.  Maybe more, maybe less.

But one shouldn't design their buffers based on the total lumped
capacitance.  If a buffer has a 1ns rise time, anything that is more than
three inches away, isn't even "seen" by the buffer until it has already
finished slewing.  You need to treat these nets as distributed lines with
occasional lumped loads hung on them.

Neither PCI nor PCI-X limits you to four slots.  By trading off clock speed,
for example, a system designer could build a box with a dozen slots on one
bus.  How would your ASIC vendor handle the fact that your IC might drive
anywhere from one to a dozen loads?  Don't think of the loads as a single
lumped capacitance.

Regards,
Andy

application/ms-tnef