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RE: PCI-X Bus loading in Pf
> The only number I question is the 3pf
> / inch for traces. My board guy says that for our 12 layer impedance
> controlled boards, it is much less than 1 pf / inch.
The formula for distributed capacitance is Co = Td/Zo where Co is
capacitance per unit length, Td is delay per unit length, and Zo is
characteristic impedance of the trace.
PCI 2.2 specifies Td = 150 - 190 ps/inch, and Zo = 60 - 100 ohms, on plug-in
cards. PCI-X is the same except Zo is reduced to 57 ohms +/- 10%. With
average numbers, I get 2.1 pF/inch for PCI and 3.0 pF/inch for PCI-X The
minimum possible Co would be 1.5 pF/inch for PCI, 2.4 pF/inch for PCI-X. To
get much less than 1 pF/inch, either the traces are too skinny or the
dielectric constant too low, resulting in the impedance much too high and/or
the delay out of range.
Is it possible your board guy meant a little less than 1 pF/cm ? That would
be OK for PCI.
> New question- Is it acceptable for me to send the vendor the PCI-X specs,
> or are they required to join the SIG to get them?
They do not need to join the SIG to get the specs, but they should purchase
them. The spec isn't exactly in the public domain; but the price is
reasonable ($25 a copy plus shipping). I don't know about giving them just
the pages they need; personally I think they should have their own copy.
> I was thinking of faxing
> just the I/O pages to the engineer who is doing the work- That would be
> easier then him convincing his management to release funds, cutting a PO,
> Thank you for you help!
> Brent Barr
> > -----Original Message-----
> > From: Ingraham, Andrew [mailto:Andrew.Ingraham@compaq.com]
> > Sent: Thursday, June 14, 2001 7:44 AM
> > To: email@example.com
> > Subject: RE: PCI-X Bus loading in Pf
> > I would be wary of using a buffer designed on the basis of only a simple
> > XpF load, especially at PCI-X speeds. Real loads aren't like that, and
> > seems inappropriate to define a buffer on the basis of such a load when
> > pushing 133MHz switching speeds.
> > I might also be rather wary of an ASIC vendor that refuses to make a
> > buffer (one that meets the PCI-X specs). You might consider changing
> > vendors to one that supports PCI-X, thereby sending a message to the
> > vendor that they are out-of-step.
> > Both PCI and PCI-X define minimum and maximum drive strengths (in the
> > of V/I curves), slew rates, and timing specs into specified test loads.
> > Your ASIC vendor does not need to "perfectly match" the curves! The
> > curves are limits. All they need to do is fall within the curves.
> > it is more difficult to do this for PCI-X than it was for PCI, because
> > PCI-X curves are closer together, that's what you pay in order to get
> > higher speeds.
> > What is a realistic capacitive load to assume for a PCI-X bus? Since at
> > 133
> > MHz it is only a single slot, my guess is 8pf for the other end, 4pf for
> > the
> > slot, plus the 8pf at the source puts me at about 20pf. At 100Mhz with
> > two
> > slots I get about 32pf.
> > If you really want round numbers ... each PCI-X IC can have an input
> > capacitance at its pins of up to 8pF. 10pF for a PCI IC. Remember that
> > you can plug a PCI card into a PCI-X slot, or vice-versa, but of course
> > won't be running at 133MHz.
> > I didn't think it was customary to count the capacitance of the driving
> > IC, when you sum the total load capacitance driven by an output buffer.
> > I have seen values of around 2-3pF for the PCI/PCI-X connector itself.
> > Traces are about 3pF/inch. They might be as much as 2.75 inches long
> > (about 8pF) on each PCI-X card. Figure about an inch between each slot
> > the motherboard, plus unknown lengths to the slots from the host bridge
> > plus any other PCI/PCI-X devices on the motherboard. So a 4-slot system
> > might have a total capacitance approaching 100pF. For a 1-slot bus,
> > 20-35pF. Two slots, 35-55pF. Maybe more, maybe less.
> > But one shouldn't design their buffers based on the total lumped
> > capacitance. If a buffer has a 1ns rise time, anything that is more
> > three inches away, isn't even "seen" by the buffer until it has already
> > finished slewing. You need to treat these nets as distributed lines
> > occasional lumped loads hung on them.
> > Neither PCI nor PCI-X limits you to four slots. By trading off clock
> > speed, for example, a system designer could build a box with a dozen
> > on one bus. How would your ASIC vendor handle the fact that your IC
> > drive anywhere from one to a dozen loads? Don't think of the loads as a
> > single lumped capacitance.
> > Regards,
> > Andy