I am making a design involving PCI interface targeted at Altera chip for 66MHz. But we have a ready board with Altera 10K chip for 33MHz. After fitting we found that the design setup time is not met for 33MHz. We just want to use the 33MHz board to test its functionality before 66MHz board is manufactured. To reach our goal, we have an idea to reduce PCI clock from 33MHz to 25MHz so that my new design will meet its setup time and we can start debugging my design functionality with the ready board.
For 33MHz PCI clock, 30.30ns clock period, 7ns setup time, 11ns Tval time;
For 25MHz PCI clock, 40ns clock period, keeping Tval and Tprop unchanged, I can get extended setup time 16.70ns. Is it right?
Any comments related with reduced PCI clock frequency are appreciated.
Micro Memory Inc.
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