|
Hi,
I have been designing a 66/64 PCI interface and now
is trying to fit my design into a Altera 20K chip.
After some efforts, we found PCI interface AD pins
Tco(clock to output) is at 13ns level. It is due to AD_OE delay. AD_OE has to
drive 64 pins at the same clock, no ways to shorten its Tco by placing near
all pins. An engieer from Altera suggested me to assert 1 clock before AD data
is sent to AD.
The following is an exerpt from his
email:
"If you are unable to place both the OE reg and the
OUTPUT reg near the pin to meet timing, what you might have to do is assert the
OE signal one clock earlier to when the data is asserted.
Since
your design will own the bus, you should be able to assert the OE signal without
any problems, and then on the next clock edge your data can be successfully
transferred onto the bus meeting all Tco requirements."
I would like to carefully listen to everyone's
opinion and experiences on whether his method is workable or any other
tricks, for example, using reverse clock to get another half clock time for
AD_OE. Weng Tianxiang
Micro Memory Inc. 9540 Vassar Avenue Chartsworth, CA 91311 Tel: 818-998-0070 Fax: 818-998-4459 |