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RE: IO space devices
I am not familiar with how much background you have in the operation of I/O
devices so please forgive me if this information is too basic for you or
redundant review of PC System architecture.
I am not terribly familiar with adapters for the most part. My work
involves BIOS engineering for motherboards and system devices. With this in
mind I can provide you with some information on motherboard devices which
typically consume I/O registers.
Numerous system devices utilize I/O Space. There are generally several
categories of systemboard I/O space consumers:
1. Motherboard chipset devices at fixed addresses. Typically ISA legacy
2. ISA Bus peripheral devices at fixed addresses. Typically Super I/O.
3. Chipset devices with relocatable I/O space requirements
Motherboard Devices at Fixed Addresses
These are typically integrated onto the system chipset.
The north bridge typically contains the two fixed DWORD I/O Ports for PCI
CSAM mechanism at CF8h and CFCh.
Most of the legacy devices are incorporated in the south bridge or I/O
Controller Hub PCI-to-ISA Bridge Function. This is PCI Function 0 on PIIX4
- ISA Bus embedded devices: Keyboard Controller
Real Time Clock
All of these devices consume I/O space resources at fixed addresses
typically below 0100h without also using memory space. Several of the
devices also use IRQ and DMA resources.
ISA Bus Peripheral Devices
These are accessed through the chipset PCI-to-ISA Bridge but are contained
on separate silicon devices such as Super I/O controller. This typically
includes LPT port, COM ports, Keyboard Controller.
- LPT port at 378h, 278h
- COM ports at 2F8h, 3F8h
- Keyboard controller at 60h & 64h
Both of these categories hearken back to the original 8086 and IBM PC system
design and therefore require fixed I/O space address for backward
compatibility. Therefore for compatibility reasons they can not be
relocated in I/O space or memory mapped for access in the CPU I/O space.
Relocatable I/O Space Registers
The same chipset silicon (actually PCI functions within the chipset silicon)
also consume I/O space addresses which are relocatable in memory via a Base
Address Register. Each chipset PCI function typically utilizes a separate
set of contiguously located I/O space registers accessed via a programmable
Base Address Register which is itself located in the PCI Configuration Space
for that function. This BAR is typically reprogrammed from power up
defaults by the BIOS or possibly the O/S after bootstrap loading to relocate
the I/O space registers anywhere in the CPU I/O space after boot.
All of the PCI functions in the chipset (both north bridge and especially
south bridge) also use I/O port ranges with programmable base addresses.
South Bridge (PIIX4) given exempli gratia:
PCI Function 0: PCI-to-ISA Bridge
PCI Function 1: IDE Controller
PCI Function 2: USB Host Controller
PCI Function 3: Power Management (APM & ACPI)
All of the registers in these categories would be described in the data
sheet for the system chipset.
Hope this information helps. Please feel free to contact me with any
From: Marco Serafini - QR s.r.l [mailto:email@example.com]
Sent: Thursday, July 12, 2001 12:03 AM
To: Ryan Mcdaniel; firstname.lastname@example.org
Subject: Re: IO space devices
> What kinds of devices normally use IO space?
> I know IDE bridges do. What else? Do any devices
> always use IO space without the capability of
> using memory space or might there be newer versions
> which allow use of memory space instead?
> Ryan McDaniel