RE: pci clock frequency

["Ingraham, Andrew" <Andrew.Ingraham@compaq.com>]

> I am confused by how to chang clock frequency.
> Someone say : "on a pci bus with a clock fequency between 33.3MHZ and
> 66.66MHZ,the pci rst# signal must be 
> asserted before a clock frequency change is made."
> Someone say:"The 66MHZ specification states that the clock frequency may
> be changed at any time as long as 
> the clock edges remain clean and the minimum high and low times are not
> violated."
> Could you tell me which statement is correct?or the correct methord how to
> change the clock frequency .
 
Neither is quite correct, but the first essentially got it right.

For 33MHz PCI (0-33.333MHz) only, the clock frequency may be changed at any
time, even on a cycle-by-cycle basis, as long as it remains clean, the clock
period never drops below 30.0ns, minimum high and low pulsewidth
requirements are met, and if it fully stops, it may only stop in the low
state.

For 66MHz PCI (33.333-66.667MHz), a change in clock frequency must be
accompanied by a PCI Reset, which must be asserted *while* the clock
frequency change is being made.  Thus, one should (1) assert RST#, (2)
change the clock and wait for it to settle and then for Trst-clk to expire,
and then (3) de-assert RST#.  If you did steps (1) and (2) at the same time,
I'm not sure anyone would tell the difference.  The important thing is to
leave RST# asserted after changing the clock frequency, to give each PCI
device a chance to lock-up to the new frequency and then re-initialize
themselves.

"Spread spectrum clocking" may also be used, without asserting RST#
continuously.

Get yourself a copy of the PCI Spec.  Don't work on the basis of rumors.

Regards,
Andy