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RE: Glitching of PCIRSTN



hi all,

you touched a common problem in any ASIC design using
an asynchronous reset signal to put the design to a
known state.
the details are clear:
- reset must effect the FFs immediately (asnchronously)
- rising edge of reset must be kept away from rising
  edge of clock

the following lines of code are representing the solution
we are using in our company as a kind of standard:


-- this is the reset generator:
--                      ___     ___     0
-- (1) ----------------|   |---|   |-----|\ 
--                     |   |   |   |     | |-- (nRESETInternal)
--                    -|>__|  -|>__|   --|/
--                   |   O   |   O    | 1 |
-- (nRESETGlobal) ___|___|___|___|____|   |
--                   |       |            |
-- (Clock) __________|_______|       (ScanMode)
--
-- as soon as nRESETGlobal becomes 0 nRESETInternal is (re)set
-- to 0 as well (with a minimal R-to-Q delay)
-- after nRESETGlobal has been deactivated the (1) ripples through
-- the registers and nRESETInternal is asserted to 1 definetly
-- AFTER the rising edge of Clock (CK-to-Q delay of FF, for all
-- ASIC technologies we have been using so far this delay
-- is larger than the R-to-CK timing requirements)
-- two registers generally are suffucient to keep metastability
-- effects away from the following logic
-- the mux at the end is intended to distribute the external reset
-- instead of the internal to the FFs in the scan pathes during
-- scan mode since the internal reset is considered to be un-controllable

ResetGen : Process(nRESETGlobal , Clock)
begin
  if (nRESETGlobal = '0') then
    nSyncReset = (others = '0');
  elsif (Clock'event and Clock = '1') then
    nSyncReset  = nSyncReset(0) & '1';
  end if;
end process;

nRESETInternal = nRESETGlobal when (ScanMode = '1') else nSyncReset(1);

-- all other FFs in the design are using the
-- nRESETInternal signal as asynchronous reset

AnyProcess : Process(nRESETInternal , Clock)
Begin
  if (nRESETInternal = '0') then
     -- initialization code
  elsif (Clock'event and Clock = '1') then
     -- register values
  end if;
end process;

of course you must exclude the nSyncReset-FFs from scanpath
insertion and you will have to bypass the ResetGen logic in scan
mode in order to keep the FFs connected to the nRESETInternal signal
scan-testable (as shown above).

just to give an idea of a possible solution.
as i said, this works well for our designs.

best regards

  olaf

-- 
Olaf Reichenbaecher
Senior Design Engineer
_____________________________
sci-worx GmbH
Garbsener Landstr. 10
30419 Hannover
Germany
Tel +49 (0)511 277-1432
Fax +49 (0)511 277-2410
Olaf.Reichenbaecher@sci-worx.com
www.sci-worx.com