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RE: Glitching of PCIRSTN
Good point!!! I really miss the point when nRESET has a short glitch.
It will take one day or more for me to give a correct answer.
From: Neal Palmer [mailto:firstname.lastname@example.org]
Sent: Tuesday, November 27, 2001 6:54 PM
To: Weng Tianxiang
Subject: RE: Glitching of PCIRSTN
you missed the problem of "Glitching of PCIRSTN" in your logic. If
you get a short glitch of PCIRSTN way after (5 clock cycles or more) the
initial deassertion, then you are back to the problem of having only
some of your FFs reset.
On Tue, 27 Nov 2001, Weng Tianxiang wrote:
> Hi Andrew,
> Thank you for your comments.
> The following is the part of my new code in VHDL that absorbs your and
> Neal's advices. I think it will be benefitial to any PCI core
> -- at concurrent space
> nRESETGlobal <= nRESET and nRESETBuffer(4);
> -- for any FF signals
> AnyProcess : Process(nRESETGlobal, CLK66M)
> if(nRESETGlobal = '0') then
> -- initialization code
> elsif(CLK66M'event and CLK66M = '1') then
> -- register values
> end if;
> end process;
> -- nRESETBuffer(4) is used as internal nRESET deassertion synchronous
> signal nRESETBufferA : Process(CLK66M)
> if(CLK66M'event and CLK66M = '1') then
> nRESETBuffer(4 downto 0) <= nRESETBuffer(3 downto 0) & nRESET;
> end if;
> end process;
> 1. What cause us to worry about nRESET is the rising edge of nRESET
> that may happen at the same time or very close time range with clock
> rising edge, generating metastability situation with FF. Shift
> register eliminates the situation.
> 2. nRESETGlobal signal is an "AND" operation that guarantees that
> nRESET assertion will be immediately effective while its rising edge
> is masked by synchronous signal nRESETBuffer(4), leaving no any clock
> free running for other FF.
> 3. After PCI normal operations, re-assertion of nRESET will cause no
> trouble. The reason is nGNT will be first deasserted to any PCI
> boards, leaving all PCI master to linquish PCI bus first.
> 4. I only use nRESET signal as nREQ_OE signal. Other OE signals
> driving to PCI bus has more complex logic, but no nRESET is directly
> Any comments and advices are welcome.
> -----Original Message-----
> From: Ingraham, Andrew [mailto:Andrew.Ingraham@compaq.com]
> Sent: Tuesday, November 27, 2001 1:02 PM
> To: Weng Tianxiang
> Cc: email@example.com
> Subject: Re: Glitching of PCIRSTN
> > The method I will use to get around the situation is to use a 5
> > levels
> > of shift registers as nRESET buffers and use the 5th FF signal as
> > global synchronous reset signal ...
> I think you want to use the OR of both the raw RESET and the
> shifted/synchronized version.
> Or connect the raw version to your output buffer tri-states, and the
> sync'd version to your state machine logic.
> You need your ASIC to go into Reset immediately when nRESET does
> assert. Especially important that your outputs tri-state and get off
> the bus right away (see the "Trst-off" spec) and not wait for 5 more
> clocks to come, which may or may not happen for a while if at all.
-- Neal Palmer
The Dini Group
1010 Pearl St #6
La Jolla, CA 92037
(858) 454-3419 x16
(858) 454-1728 (Fax)