PCI-X Attribute Phase Reserved Bits

[Espen Bøch <espen@vmetro.no>]

Gentlemen,

In the PCI-X specification v1.0a, chapter 2.10.3 Split Completion
Address, page 81, the Split Completion address phase is defined. The 7
lower bits of the address are either reserved, or copied from the address
field of the Split Request. This is done to enable bridges and targets to
keep track of where the transaction starts relative to an ADB.

My question is: Why are these bits reserved, and not always
driven?

It seems to me that having these bits reserved cause the design to be
much more complicated. I will illustrate why by the following two
examples:

Example 1:
1. An initiator issues a DWORD read from a target at address 0x10000004.
The target responds with Split Request, and thus becomes a
completer.
2. The completer issues a Split Completion with the lower 7 bits of the
address = 0, as required by the spec.
3. When the initiator receives the data, it can not use address bit 2 to
direct the data to an odd memory location (where it actually belongs). It
has to KNOW that the request was from an odd address, and place the data
accordingly.


Example 2:
I have seen three different devices now at two different locations that
do not obey the spec at this point. One is a P2P bridge, the two other
are plug in cards.
In the case of the bridge, the following happens:

1. An initiator issues a DWORD read from a target at address 0x10000004.
The target resides behind a bridge.
2. The bridge issues a Split Request on the primary side, and issues a
new DWORD read on the secondary side.
3. The target responds with Split Request, and thus becomes a
completer.
4. The completer issues a Split Completion with the lower 7 bits of the
address = 0x04, thus violating the spec at this point.
5. The bridge accepts the Split Completion on its secondary side
6. The bridge issues a new Split Completion on the primary side, but now
has REQ64# asserted, but still byte count = 4.
--> The data has now "disappeared", and the data presented
by the birdge is corrupted.
7. The Initiator claims the Split Completion and stores the corrupted
data presented by the bridge on AD(31:0)

Apparently the bridge used the reserved bits in this case, and the result
is corrupted data.


Has anyone else seen these problems with PCI-X devices out there? Can
someone explain the reasoning behind the reserved bits? Why are they
reserved? Would it not make life a lot easier to designers if AD(6:0)
always contained a valid 7-bit address for Split Completions?


Thanks in advance for your help.


Best Regards,

Espen Bøch.

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Espen Bøch                       Phone: +47 - 22 10 60 90
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