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Transaction ordering - reads flushing writes
I was wondering about the some of the transaction ordering
rules on PCI. Particularly, I was wondering why a read from
a processor on the host side of a host PCI bridge which is
reading some target on the PCI side should flush writes coming
from a PCI master on the other side of the bridge which are destined
for the SDRAM on the host side.
I might be able to think of a few scenarios, but I am not
sure if any of them are used in real systems. Can anyone provide
an example where this is absolutely necessary using a common
PCI bus mastering device(hard drive, ethernet, etc.)?
Imaging Systems Division