Re: Transaction ordering - reads flushing writes

["Richard Iachetta" <iachetta@us.ibm.com>]

>I was wondering about the some of the transaction ordering
>rules on PCI. Particularly, I was wondering why a read from
>a processor on the host side of a host PCI bridge which is
>reading some target on the PCI side should flush writes coming
>from a PCI master on the other side of the bridge which are destined
>for the SDRAM on the host side.

Let's say the PCI adapter (network card, scsi hard drive or whatever) dumps
a block of memory into host memory.  When it is done, a status bit gets set
in the adapter indicating that the write has complete.  However, because
bridges post write data, there may be a bunch of data still in write
buffers in the bridge which hasn't made it out to host memory.  When the
host CPU reads that status bit in the PCI adapter's register space to find
out if the data is present, the read data will tell it that the data is
there.  If there were no requirement that the read flush the writes, the
CPU could be told that the data is in host memory while really some of it
is still in the bridge's posted write buffers.  If that happens the host
CPU may read garbage data when it accesses that data block.

Another thing to consider, the PCI target may have been behind a PCI2PCI
bridge after the host PCI bridge.  Now, his writes to host memory may be
spread between the write buffers of two bridges.  The PCI ordering rules
ensure that a read to that target pulls the writes out of all bridges so
that the target's reported status will be accurate information.

Rich Iachetta
IBM Microelectronics Division -- Austin
World Wide Field Design Center
Phone: 512-838-6305   Tie Line: 678-6305