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Re: FW: [Fwd: ground perforations in two-layer boards]
The story I heard from one PCB vendor was that a solid copper plane would
tend to excessively concentrate current during the electroplating of copper
into the holes, used as vias and for component leads, between the two
sides. Generally speaking a constant density of copper is desired
throughout the board areas on both sides of the board for this process.
Ground perforations improve this situation.
Regards,
John Venious
Director of Technology
Acromag, Inc. http://www.acromag.com
30765 S. Wixom Rd., Wixom, MI 48393-7037
Phone 248-624-1541 FAX 248-624-9234
Jim Fisher
<JFisher@icsme To: "'pci-sig@znyx.com'" <pci-sig@znyx.com>,
dical.com> "'john.billingsley@amd.com'"
<john.billingsley@amd.com>
12/07/01 12:36 cc:
PM Fax to:
Subject: FW: [Fwd: ground perforations in
two-layer boards]
-----Original Message-----
From: Jim Fisher
Sent: Friday, December 07, 2001 11:10 AM
To: 'api@art-render.com'; ',pci-sig@znyx.com'
Subject: RE: [Fwd: ground perforations in two-layer boards]
I think some things are being mis-understood. Let's take a specific
example.
If you are designing a 2 sided board where most of your signals are routed
on one side, and you desire a ground plane on the other side of the FR4
core, you would probably end up with more copper being etched from the
signal side. A PCB house will try and balance the copper ratio from side
to
side in one of two ways. They may ask if it is OK to perforate the ground
plane side. Or, they may ask if they can fill in the other side as much as
possible with copper that is probably left flapping in the breeze
(electrically speaking that is). They should also ask you about controlling
impedance. When you fill in copper on the top side you probably want to
tie
the filled areas to ground with some vias to the back side. As someone
else
pointed out in a response email, you will also have to take care in
balancing additional ground next to signal traces with your desired
impedance. Most PCB houses are capable of helping you figure this stuff
out.
As for controlled impedance with a perforated plane, it is best to try and
balance the other side of the core with copper as much as possible during
layout. In doing so, you will have a more balanced layout (copper content
that is on both sides of the core) and not be asked / requried to punch
holes in your copper to achieve uniform plating between sides. By the way,
most boards have 1 ounce copper on each side. I don't remember how the
weight is determined but more ozs. require different etching times than 1
ounce. This is something that a PCI card designer should never have to
worry about because you would probably be using 1 ounce layers at all
times.
2-3 oz layers are typically used in backplane designs for power / ground
planes. John Billingsley's email discusses this concept of flooding layers
with copper.
Correction from previous email:
Etching time, as best I can recall is dependent upon the amount of copper
on
the surface and its thickness. If one side has less to etch away than the
other side, it will be done sooner that the side that has more to remove.
(I stated this incorrectly in the first email). To compensate, a PCB house
will let the board sit in the etch tank a little longer. Due to tolerances
of trace width and thickness they can play some games to get things to work
out. As long as they stay within the tolerances (Impedance) specified,
then
all is well as long as the traces that may be present on the heavier copper
side are not over etched.
The moral of the story is:Balance the amount of copper on your layers as
best you can between the top side and bottom side of your board. For
longer
boards, this will also help prevent warping which can also occur due to
imbalance. My best recollection about board warp is that a board will warp
in a concave manner for the side with the least amount of copper. Board
warpage is more evident with multiple layers.
The above information is based on my experience as a HW mgr and having
workded with PCB fabricators. I also want to say that I am not an expert
in
this arena. If further information is of interest, I can probably find an
explaination from a source with expertise. You would rather hear it from
the horse's mouth rather than the other way. I am probably more associated
with the other end when it comes to this subject.
Thanks,
Jim Fisher
-----Original Message-----
From: Andrew Ircha [mailto:api@art-render.com]
Sent: Friday, December 07, 2001 10:46 AM
To: pci-sig@znyx.com
Subject: [Fwd: ground perforations in two-layer boards]
I would have thought a few perforations here and there is not going to
make a calculable difference to impedance - in any case the PCI range of
impedance is comfortably within the easy grasp of most PCB processes
without resorting to such techniques.
If you are making two sided PCBs wouldn't you use two sided material
(i.e. FR4 with copper on both sides)? In which case why would you buy it
with heavier copper on one side rather than the other? I take the point
though that both side will need different processing and over etch is a
possibility. It sounds like the perforations are there to help the PCB
process. Perhaps they are visually inspected for evidence of
over-etching?
Cheers,
Andrew Ircha
Jim Fisher wrote:
>
> If I remember information from a tour of a PC fab facility correctly,
when
> you are in the etch tank and one side of your board has a radically
> different amount copper on it than does the other side, you are in a
> situation where the amount of time to etch is different for each side.
The
> longer time to etch is of coarse on the heavier copper side. That is not
a
> good situation for the other side of the baord in that you may over etch.
> Therefore, by placing holes in the side with more copper (your ground
plane)
> helps bring the ratio of copper to etch from both sides to be roughly the
> same. You will then have a higher yield on your PC bd from the fab
house.
>
> Thanks,
>
> Jim Fisher
<snip>
> Perhaps the holes are there for impendence control reasons since the
board
> thickness
> is large. Or, is it an EMC issue ?