Dear PCI experts,
The electrical spec (Pci rev 2.2) recommend that PCI components on a universal board must use dual voltage I/O buffers, powered from "I/O" designated power pins.
In my PCI universal card I'm using a PLD (FPGA device) and to implement a fully-compliant solution I provide two separate configuration files (for 5V system I want 3.3 I/O clamp diode to be off) and some logic to load the correct config file to assure compliance with either the 5V or 3.3V signaling environment.
My FPGA is powered by 3,3V supply and can drive and be driven by 3.3V or 5.0V devices. So nowadays 3.3V components usually operate in a 5V signaling environment contrary to the PCI spirit.
Any comments about this matter?
Now my question is: in a new universal board can I leave unused dedicated Vi/o pins on the PCI edge connector (properly decoupled to the ground plane) and use only the 3.3V supply from the PCI connector (or 5V supply with a regulator) to power up the PLD? I've got to know different strategies, which one do you suggest for a compliant PCI universal board?
Thanks for any suggestions.
Marco Serafini - QR s.r.l.