Re: NMI/parity error

[Carter Buck <CBuck@PLXTech.com>]

Mikhail,

Please ensure that the PCI 2.1 Features Enable bit is set (MARBR[24] = 1) 
either in EEPROM or by local host configuration.  Setting this bit enables 
the 8- and 16- PCI clock rules, delayed reads, and 2^15 PCI clock timeout 
on retries.

Regards,

Carter Buck
Technical Applications Engineer
PLX Technology, Inc.
(408) 328-3513

At 04:54 PM 12/21/01, Mikhail Matusov wrote:
>Hi all,
>
>I am having a weird problem in a cPCI system, which I don't know how to
>debug. Here it goes:
>
>The system is a Teknor chassis with a Teknor cPCI-MXS64 CPU + a peripheral
>card that I designed, running Windows2000. The peripheral card has the PLX
>PCI9054 bridge and the TMS320C6203 DSP chip. The host can talk to the host
>port of the DSP through the PCI bridge. Now the problem: if the DSP does not
>supply READY signal to the PCI controller for too long (why it does so is a
>different story) the whole system crashes into the Blue Screen saying
>something like NMI/parity error.
>
>I was able to reproduce exactly this kind of crash by forcing the PLX chip
>to generate SERR signal, however neither SERR nor PERR appear to be asserted
>during the real crash.
>
>Any ideas are highly appreciated.
>
>Thanks,
>============================
>Mikhail Matusov
>Hardware Design Engineer
>Square Peg Communications
>Tel.: 1 (613) 271-0044 ext.231
>Fax: 1 (613) 271-3007
>http://www.squarepeg.ca