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Re: NMI/parity error
probably your getting a master abort on the PCI bus in case the DSP does not
respond within time.... I.e. the PLX chip will signal retries on PCI in case
you do not assert RDY on the locla DSP bus in time. In consequence, the
master on PCI (I.e. Teknor CPU) will repeat the cycle on PCI again and
again... but it is still getting retries. The master will not repeat the
cycle forever (limit: 2^15 or 2^25 PCI clocks typ.), but will discard the
pending transaction some time. This causes the NMI. This is happening on the
local bus of the CPU. That's why you do not see SERR asserted on the
I assume the Teknor CPU has a Pci2PCI bridge onboard that connects the CPUs
local PCI bus and the CPCI backplane. PCI2PCI bridges usually signal SERR on
the primary bus if they discard a transaction on the secondary bus.
Moreover, if the PLX chip does not follow the 16/8 clock rule (cf. mail from
Carter Buck) the P2P bridge will behave differently on its secondary bus,
but behave the same on the primary. Same result: SERR active. Blue screen.
You may disable SERR signaling of the bridge through its config spacve
register set. This is a solution for the lab only to proceed with testing.
Moreover, you will get stale data on either the host or the dsp.
Your PCI system is behaving as intended. It's the dsp that's crashing the
----- Original Message -----
From: "Mikhail Matusov" <email@example.com>
Cc: "PICMG EMAIL REFLECTOR" <firstname.lastname@example.org>
Sent: Saturday, December 22, 2001 1:54 AM
Subject: NMI/parity error
> Hi all,
> I am having a weird problem in a cPCI system, which I don't know how to
> debug. Here it goes:
> The system is a Teknor chassis with a Teknor cPCI-MXS64 CPU + a peripheral
> card that I designed, running Windows2000. The peripheral card has the PLX
> PCI9054 bridge and the TMS320C6203 DSP chip. The host can talk to the host
> port of the DSP through the PCI bridge. Now the problem: if the DSP does
> supply READY signal to the PCI controller for too long (why it does so is
> different story) the whole system crashes into the Blue Screen saying
> something like NMI/parity error.
> I was able to reproduce exactly this kind of crash by forcing the PLX chip
> to generate SERR signal, however neither SERR nor PERR appear to be
> during the real crash.
> Any ideas are highly appreciated.
> Mikhail Matusov
> Hardware Design Engineer
> Square Peg Communications
> Tel.: 1 (613) 271-0044 ext.231
> Fax: 1 (613) 271-3007