Can non-prefetchable memory reads/writes be combined by bridges?

[Alan Hall <alan@databuzz.co.uk>]

Dear Group,

I'd be grateful if someone could clarify the following for me:

I am designing a 33/32 PCI target device with memory mapped I/O 
resources, i.e. the resources are declared as non-prefetchable memory in 
the BAR configuration. I can't figure out if my backend needs to cope 
with burst accesses. Although the software will only make discrete 
accesses to individual target addresses, I am unclear whether a bridge 
might combine fast sequential accesses into short bursts for either 
reads or writes.

It's quite likely that a particular software sequence could well write 
to 2 consecutive addresses in succession, and at modern processor speeds 
both of these writes will occur in a short timescale compared to the PCI 
execution speed.

I know that "combining" is permitted for consecutive writes to 
prefetchable memory, but am not clear whether it is allowed, or happens 
in practice, for non-prefetchable memory writes, or for reads to either 
sort of memory.

Hope I have been clear!

TIA
-- 
Alan Hall, Ipswich, UK