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Can non-prefetchable memory reads/writes be combined by bridges?
- To: PCI-SIG@znyx.com
- Subject: Can non-prefetchable memory reads/writes be combined by bridges?
- From: Alan Hall <firstname.lastname@example.org>
- Date: Mon, 7 Jan 2002 23:16:43 +0000
- Resent-Date: Mon, 7 Jan 2002 15:29:17 -0800
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I'd be grateful if someone could clarify the following for me:
I am designing a 33/32 PCI target device with memory mapped I/O
resources, i.e. the resources are declared as non-prefetchable memory in
the BAR configuration. I can't figure out if my backend needs to cope
with burst accesses. Although the software will only make discrete
accesses to individual target addresses, I am unclear whether a bridge
might combine fast sequential accesses into short bursts for either
reads or writes.
It's quite likely that a particular software sequence could well write
to 2 consecutive addresses in succession, and at modern processor speeds
both of these writes will occur in a short timescale compared to the PCI
I know that "combining" is permitted for consecutive writes to
prefetchable memory, but am not clear whether it is allowed, or happens
in practice, for non-prefetchable memory writes, or for reads to either
sort of memory.
Hope I have been clear!
Alan Hall, Ipswich, UK