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<TITLE>non-prefetchable 64 bits memory bars in PCIX</TITLE>
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<P><FONT SIZE=3D2 FACE=3D"Arial">Hi,</FONT>
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<P><FONT SIZE=3D2 FACE=3D"Arial">PCIX</FONT><FONT SIZE=3D2 =
FACE=3D"Arial"> requires all memory bars to be 64 bits bars</FONT>
<BR><FONT SIZE=3D2 FACE=3D"Arial">PCI-X 1.0, section 7.1, item 3, =
sentence 1, page 137: "All Base Address register, except the =
Expansion ROM Base Address register, that request ***memory*** =
resources must support 64-bit addressing as described in PCI 2.2 =
..." (My emphasis).</FONT></P>
<P><FONT SIZE=3D2 FACE=3D"Arial">From the other hand, there is no =
memory (non prefetchable) Base and Limit upper 32 bits registers as for =
prefetchable memory in PCIX bridges (As for PCI bridges).</FONT></P>
<P><FONT SIZE=3D2 FACE=3D"Arial">Does it implies that memory (non =
prefetchable) bars can be only 32 bits?</FONT>
<BR><FONT SIZE=3D2 FACE=3D"Arial">Regards,</FONT>
<BR><FONT SIZE=3D2 FACE=3D"Arial">Noam Bloch</FONT>
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