RE: PCI Interrupt and Acknowledgement

["Weng Tianxiang" <WTX@umem.com>]

Hi,
Interrupt drivers are linked in priority orders in operating system.
That means two things:
1. Lower priority driver may be interruptted by higher priority
interrupt;
2. Pending higher priority drivers will get first response chance than
pending lower priority drivers.

You may change your interrupt driver's interrupt priority to get your
target met. The highest number may be 32 and lowest number is 0. Please
read related reference materials. Because NT system is not a real time
operating system, the value you select is very important regarding to
the interrupt response time. If the priority number is selected too
high, it will hang system, if too low, there may be no effect to improve
the interrupt response time.

Weng Tianxiang

wtx@umem.com
wengtianxiang@yahoo.com

Micro Memory Inc.
9540 Vassar Avenue
Chatsworth, CA 91311
Tel: 818-998-0070
Fax: 818-998-4459



-----Original Message-----
From: tjm@codegen.com [mailto:tjm@codegen.com] On Behalf Of Thomas J.
Merritt
Sent: Monday, February 04, 2002 6:43 AM
To: I. Servan Uzun
Cc: pci-sig@znyx.com
Subject: Re: PCI Interrupt and Acknowledgement


|<><><><><> Original message from "I. Servan Uzun"  <><><><><> Hi,
|
|I am using Altera' s 64-bit 66MHz PCI Megacore in my project. I 
|implemented an interrrupt & acknowledgement logic as follows,
|
|    1-) When the process is completed, an interrupt signal is generated

|and fed to pci megacore function.
|    2-) When my software that is running on the computer catches the 
|pci interrrupt, it sets a predefined bit of a register (in fpga) in 
|order to acknowledge the interrupt.
|    3-) When I check this timing by a logic analyzer, I found that it 
|is 8 microseconds between the rising edge of the interrupt signal and 
|the rising edge of int-acknowledge signal. This means that it takes 8 
|usec to acknowledge the interrupt.
|
|My question is that is this time is normal or long?

I would say that this is pretty normal.  It depends upon a number of
factors, like the type and speed of CPU, the type and speed of memory,
the host bridge chipset and most importantly the operating system that
you are using and the design of your device driver.

|                                                    Is it possible to 
|shorten this interrupt acknowledgement time?

It depends upon how many of the above variables you can control.  I
would not expect too much though.  Interrupt service routines are likely
to miss in cache when accessing memory and these cache misses are
costly.  The fewer memory or PCI accesses you do in your device driver
the shorter your interrupt latency will be in the typical case.  Worst
case interrupt latency can be substantially longer than 8us and you may
need to size FIFOs accordingly in order for your device to function
propertly.

TJ Merritt
tjm@codegen.com
1-415-834-9111