Power Management, RST at D3hot/cold

[Lukas Reinbold <lreinbold@syskonnect.de>]

Hi experts,

for a PCI device it's a straight forward approach to reset all flops, state 
machines etc., when PCI Reset (RST#) is asserted.

Problem with that:
If power management is added, it looks like all stuff is reset, when power
is switched off going from D3hot to D3cold:
This is not what I'm expecting, because I need some of this stuff for generating 
PME#.

Separating the chip in sections being reset and others being not reset by RST
generates the question how to reset the section, which doesn't depend on RST ...

Another idea goes for disabling the RST path, if switched to D3hot, but this
looks strange also.

Another idea goes for gating off the RST path derived from a 
power-on-reset-circuit. Which power to check ? 5V, 3.3V, or VIO ?
Looks also strange, because has to react earlier than POWER_GOOG generated
on the system.

I'm not too happy with all of those ideas, so I would appreciate, if someone
could help with some hints/ideas on that ?


Lukas Reinbold

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                            Senior Hardware Engineer          

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