Can this reliably work on PCI bus?

["Mikhail Matusov" <matusov@squarepeg.ca>]

Hi all,

I have a cPCI board with a TI TMS320C6xxx DSP on it. The board is a PCI
target only and we access DSP through its host port, which is made up of two
registers: address register and data register. Thus, every transaction
splits into two: first one has to put an address into the address register
and then data can be read or written to/from the data register. Everything
worked fine till recently we started seeing some errors during read cycles.
Errors are such that occasionally we receive data from either address n+1 or
n+2. I think I have to mention that the system (into which  we plug  our
card) has a 21154 PCI-to-PCI bridge (not the latest buggy revision). My
suspicion is that because our write and read memory transactions are always
from the same address what we are seeing is some kind of transaction
reordering happening in the bridge. We tried reading address back first
before reading data from the data register, this seemed to decrease
frequency of errors but did not fix the problem completely.

So, I was wondering whether I am on the right track and whether this thing
can work at all?

Thanks,
============================
Mikhail Matusov
Hardware Design Engineer
Square Peg Communications
Tel.: 1 (613) 271-0044 ext.231
Fax: 1 (613) 271-3007
http://www.squarepeg.ca