RE: Can this reliably work on PCI bus?

["Tor Tovsland" <tor@comuniq.com>]

I have seen something similar. You have to make sure that all accesses
are finished before starting a new one, in other words all accesses
(read and write) have to be serialized. There are some "undocumented
features" with TI's HPI that can cause the behavior that you see. You
might wanto to look for high priority threads or interrupts (on host
side) that will interrupt lower priority accesses, and then switch back
to the lower priority ones again. That will make the auto-increment
feature "skip" an access, which sounds to be what you are seeing.

________________________________________________________________________
Tor Tovsland                                        Comuniq, Inc.
Sr. Software Developer, i960 Group                  2046 Samco Rd.
tor@comuniq.com                                     Rapid City, SD 57702
                                                    USA




-----Original Message-----
From: Mikhail Matusov [mailto:matusov@squarepeg.ca] 
Sent: Friday, February 15, 2002 12:23 PM
To: pci-sig@znyx.com
Cc: cpci@patriot.getnet.net
Subject: Can this reliably work on PCI bus?


Hi all,

I have a cPCI board with a TI TMS320C6xxx DSP on it. The board is a PCI
target only and we access DSP through its host port, which is made up of
two
registers: address register and data register. Thus, every transaction
splits into two: first one has to put an address into the address
register and then data can be read or written to/from the data register.
Everything worked fine till recently we started seeing some errors
during read cycles. Errors are such that occasionally we receive data
from either address n+1 or
n+2. I think I have to mention that the system (into which  we plug  our
card) has a 21154 PCI-to-PCI bridge (not the latest buggy revision). My
suspicion is that because our write and read memory transactions are
always from the same address what we are seeing is some kind of
transaction reordering happening in the bridge. We tried reading address
back first before reading data from the data register, this seemed to
decrease frequency of errors but did not fix the problem completely.

So, I was wondering whether I am on the right track and whether this
thing can work at all?

Thanks,
============================
Mikhail Matusov
Hardware Design Engineer
Square Peg Communications
Tel.: 1 (613) 271-0044 ext.231
Fax: 1 (613) 271-3007
http://www.squarepeg.ca