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PCI clock distributuion..
I've scanned the archive for my topic but didn't really find anything useful.
Perhaps you all could help me out..
We currently have a system board design which provides 8 PCI (33 MHz, 2.1) slots in
an embedded environment. There are two bridges on the backplane each of which drives
4 slots. One of the slots is used for a single board computer that drives the bridges.
It turns out that our single board computer (another vendor) is using one of the reserved pins
for the PCLK trace on one of the bridges. The SBC PCLK is routed out to the other bridge PCLK.
Now I understand since this is an embedded system, everything should be ok using that reserved pin.
BUT we are now looking to open up the system to allow 2.1+ compliant devices to be used in our slots.
A re-design is underway for the PCI backplane. Ok, now comes the questions..
What is the typical architecture to provide 8 slots in a system like this that uses a single board computer
host? To aquire 8 available PCI slots, wouldnt one need 3 bridges? One PCLK from SBC cannot drive 2 bridges.
PCLK can only drive one load.
An alternative way which, I'm sure someone has considered would be to buffer the signals so that each buffered line
can drive two bridges. The 2.1 spec doesnt really discuss buffering scenarios. But what if someone could find
buffers and design so that the timing specs were not violated?
How could all this work? What are the options and typical ways the 8 slot designs are accomplished?
Any comments on this are greatly appreciated!
Electrical Design Engineer
28775 Aurora Rd.
Cleveland, OH 44139-1891