Re: PCI clock distributuion..

[Andrew Ircha <api@art-render.com>]

Ben,

I'm no expert, but firstly PCI wasn't specified to drive more than 10
loads - an expansion card plus connector is 2 loads. This effects your
topology.

Are you certain that the SBC can only drive one bridge chip? If this
were the case, why do manufacturers offer SBC backplanes with multiple
PCI slots, all driven from one SBC. I view that as about 6 loads, all of
which get PCLK from the SBC (as the backplane is completely passive).

If loading is a problem, then keep to the loading limits and drive one
bridge chip. This bridge chip drives four slots and a further bridge
chip - assuming the bridge chip outputs a suitable PCLK copy. Then the
second bridge chip can then drive four more slots. I would think that
PCLK for anything south of any bridge chip is independant of anything
north of it i.e. each bridge chip has an 'input' PCLK independent of the
'output' PCLK - a PCI/ISA bridge chip for example doesn't have any
synchronisation between ISA and PCI. Hopefully someone will be along
shortly to contradict me if I'm wrong. That way you don't have to have a
big clock tree. I have no idea however, if this is a typical topology.

Hope that helps,


Andrew Ircha  



SBC
|
BRIDGE1
|______________________
|      |    |    |     |
slot slot slot slot BRIDGE2
_______________________|
  |    |    |    | 
slot slot slot slot

Ben Yurick wrote:
> 
> I've scanned the archive for my topic but didn't really find anything useful.
> Perhaps you all could help me out..
> 
> We currently have a system board design which provides 8 PCI (33 MHz, 2.1) slots in
> an embedded environment. There are two bridges on the backplane each of which drives
> 4 slots. One of the slots is used for a single board computer that drives the bridges.
> It turns out that our single board computer (another vendor) is using one of the reserved pins
> for the PCLK trace on one of the bridges. The SBC PCLK is routed out to the other bridge PCLK.
> 
> Now I understand since this is an embedded system, everything should be ok using that reserved pin.
> BUT we are now looking to open up the system to allow 2.1+ compliant devices to be used in our slots.
> A re-design is underway for the PCI backplane. Ok, now comes the questions..
> 
> What is the typical architecture to provide 8 slots in a system like this that uses a single board computer
> host? To aquire 8 available PCI slots, wouldnt one need 3 bridges? One PCLK from SBC cannot drive 2 bridges.
> PCLK can only drive one load.
> 
> An alternative way which, I'm sure someone has considered would be to buffer the signals so that each buffered line
> can drive two bridges. The 2.1 spec doesnt really discuss buffering scenarios. But what if someone could find
> buffers and design so that the timing specs were not violated?

The PCI spec. probably doesn't discuss buffering due to the slighly
unusual electrical requirements of PCI. 

> 
> How could all this work? What are the options and typical ways the 8 slot designs are accomplished?
> Any comments on this are greatly appreciated!