[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

PCI TRDT# & DEVSEL# timing trouble



Hello Venkat,
 
Interesting advice to drive a 1 at the end of DEVSEL# and TRDY#. ( i was sending them 'Z')But doesn't this cause trouble. Should this clock cycle be tristate so the bus can turn around ? The master will be wanting to start the next transaction by driving FRAME#, AD[31:00] and C/BE[3:0]# on the next clock.
 
Sincerely
Daniel DeConinck