Re: PCI TRDT# & DEVSEL# timing trouble

[Eric Crabill <crabill@xilinx.com>]

This advice is correct.  The control signals (FRAME#, IRDY#, TRDY#, etc...)
are defined as "sustained tri-state" signals in the spec, and it says
explicitly that you cannot simply release them by sending them to
high impedance when you are done.

You must actively drive the signal high (deasserted) to "force" it there,
for one cycle, and then in the next cycle, you can tri-state it.

Eric

> Interesting advice to drive a 1 at the end of DEVSEL# and TRDY#. ( i
> was sending them 'Z')But doesn't this cause trouble. Should this clock
> cycle be tristate so the bus can turn around ? The master will be
> wanting to start the next transaction by driving FRAME#, AD[31:00]
> and C/BE[3:0]# on the next clock.