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Decoupling capacitors

To: "PCI-SIG, Mail List" <pci-sig@znyx.com>
Subject: Decoupling capacitors
From: Iñigo Alvarez Ximenez de Embun <patxipatxi@jazzfree.com>
Date: Tue, 26 Mar 2002 21:15:34 +0100
Resent-Date: Tue, 26 Mar 2002 12:35:11 -0800
Resent-From: pci-sig@znyx.com
Resent-Message-ID: <uAbjZB.A.qcB.cpNo8@electra>
Resent-Sender: pci-sig-request@znyx.com

I'm developing a PCI board with no internal planes (only two layers). I would like to know if the decoupling requirements listed in PCI spec. are the same for 2 layers boards and for 4 or more layers boards (trace length, capacitors values, etc.)

I also would like to know if, as the PCI spec says, I can use only one capacitor for all 3.3V pins and all Vi/o unused pins.

Can anyone help me?

Thanks

Iñigo Alvarez Ximenez de Embun
e-mail: patxipatxi@jazzfree.com

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