Re: 2 layer PCI and meeting spec

[wamnet <wamnet@gte.net>]

I think this was discussed a few months ago. The PCI spec dictates that
the trace velocity be 150-190 ps/in and in the range of 60-100 ohms
which is dependent on the trace distance from a plane or copper pour.

I recall that the thread included numerous stories of two layer boards.
I remember mentioning that the two layer designs I've seen usually
employ a copper pour opposite the side that contains the traces. I
remember someone from Compaq outlining the issues of a two layer with
pour, which would lead to ~60mil distance with FR4 (Er = 4.5)

Section 4.4.3.2 discusses the issues of split planes and the effects of
signals crossing these gaps and how to stitch them with caps to provide
an AC return path.

I do know that the Intel Etherexpress cards are multi layer and
according to Jason Wright, the OpenBSD developer, these seem to work
well and hit close to the theoretical limits of the MAC/PHY's (~95Mb). 

All of the PCI boards I create, such as crypto accelerators, use a
minimum of 4 layers. A good book to get is by Dr. Howard Johnson called
High Speed Digital Design. You can get it at his website:
http://www.sigcon.com/.

Also, a few calculators for the effects of layer stack up can be found
at:


www.ultracad.com
http://www.mwoffice.com/products/txline.html

If you really want to learn more about the effects of layer stack up and
see visual 3D representation of what happens, check out
http://www.faustcorp.com/ where you can get a 2D EM simulator for free.
Also, MIT has a field solver for download.

PS: Rob - Did Mr. Moyer get you guys the older 21154BC parts I gave him?



-- 
WAM
http://home1.gte.net/wamnet
http://members.aol.com/wamnet

"Two things are infinite: the universe and human stupidity;
and I'm not even sure about the universe."
~~Albert Einstein (1879-1955)


> Subject: 
>              RE: 2 layer PCI and meeting spec
>  Resent-Date: 
>              Wed, 27 Mar 2002 05:00:00 -0800
>  Resent-From: 
>              pci-sig@znyx.com
>         Date: 
>              Wed, 27 Mar 2002 07:09:50 -0500
>         From: 
>              Rob Kellogg <RKellogg@NetOctave.com>
>           To: 
>              "'Daniel DeConinck'" <daniel.deconinck@sympatico.ca>, pci-sig@znyx.com
> 
> 
> 
> 
> Very good observations. I do not know of any specification which speaks to the number of required layers, and I looked. The closest thing to a layer specification is
>  4.3.6.1 "Routing and Layout recommendations for Four-Layer Motherboards." And these are just recommendations not requirements.
> -rgk
> 
>      -----Original Message-----
>      From: Daniel DeConinck [mailto:daniel.deconinck@sympatico.ca]
>      Sent: Tuesday, March 26, 2002 4:51 PM
>      To: pci-sig@znyx.com
>      Subject: 2 layer PCI and meeting spec
> 
>      Hello,
>       
>      Observation re 2 layer PCI:
>       
>      I can name two common devices that are sold in the tens if not hundreds of millions of units and that are 2 layer PCI boards. These would be ethernet
>      cards and sound cards. These cards sell for around $20. They need to be made dirt cheap and they need to work on a very very high percentage of
>      motherboards to avoid a bankruptcy inducing support nightmare. And they must work in conjunction with whatever else is plugged into the host PCI bus.
>       
>      So my conclusion is, that in the real world you can often ( and many do ) get away with it. 
>       
>      I am not qualified to answer the question from an engineering perspective but I would like to hear what others have to say.
>